[m-rev.] for review 2/4: Add RISC-V hardware register support (reg grades)

Paul Bone paul at bone.id.au
Fri Mar 17 14:21:28 AEDT 2023


This change enables Mercury to use the the first four caller-save
registers for its first four registers.  RISC-V has 12 caller-save
registers so we could try with more.

runtime/machdeps/riscv_regs.h:
    As above.

runtime/mercury_regs.h:
runtime/Mmakefile:
    Include machdeps/riscv_regs.h
---
 runtime/Mmakefile             |  1 +
 runtime/machdeps/riscv_regs.h | 85 +++++++++++++++++++++++++++++++++++
 runtime/mercury_regs.h        |  2 +
 3 files changed, 88 insertions(+)
 create mode 100644 runtime/machdeps/riscv_regs.h

diff --git a/runtime/Mmakefile b/runtime/Mmakefile
index d28fbbe42..be824f09c 100644
--- a/runtime/Mmakefile
+++ b/runtime/Mmakefile
@@ -151,6 +151,7 @@ MACHHDRS = \
 	machdeps/mips_regs.h			\
 	machdeps/no_regs.h			\
 	machdeps/pa_regs.h			\
+	machdeps/riscv_regs.h			\
 	machdeps/rs6000_regs.h			\
 	machdeps/sparc_regs.h			\
 	machdeps/x86_64_regs.h
diff --git a/runtime/machdeps/riscv_regs.h b/runtime/machdeps/riscv_regs.h
new file mode 100644
index 000000000..701cb92ae
--- /dev/null
+++ b/runtime/machdeps/riscv_regs.h
@@ -0,0 +1,85 @@
+/*
+** Copyright (C) 2023 The Mercury team.
+** This file is distributed under the terms specified in COPYING.LIB.
+*/
+#ifndef MR_MACHDEPS_RISCV_REGS_H
+#define MR_MACHDEPS_RISCV_REGS_H
+
+/*
+** Machine registers MR_mr0 - MR_mr36 for the RISC-V architecture.
+**
+** The first MR_NUM_REAL_REGS of these are real machine registers.
+** The others are just slots in a global array.
+**
+** RISC-V has 12 caller save registers s0 - s11.  s0 is sometimes also a
+** frame pointer.  To avoid any potential problems with s0/fp we use four
+** registers beginning at s1.  We could probably use more but I haven't
+** taken the time to test it.
+*/
+#define MR_NUM_REAL_REGS 4
+
+register	MR_Word	MR_mr0 __asm__("s1");	/* sp */
+register	MR_Word	MR_mr1 __asm__("s2");	/* succip */
+register	MR_Word	MR_mr2 __asm__("s3");	/* r1 */
+register	MR_Word	MR_mr3 __asm__("s4");	/* r2 */
+
+#define MR_real_reg_number_mr0	s1
+#define MR_real_reg_number_mr1	s2
+#define MR_real_reg_number_mr2	s3
+#define MR_real_reg_number_mr3	s4
+
+#define MR_save_regs_to_mem(save_area) (	\
+	save_area[0] = MR_mr0,			\
+	save_area[1] = MR_mr1,			\
+	save_area[2] = MR_mr2,			\
+	save_area[3] = MR_mr3,			\
+	(void)0					\
+)
+
+#define MR_restore_regs_from_mem(save_area) (	\
+	MR_mr0 = save_area[0],			\
+	MR_mr1 = save_area[1],			\
+	MR_mr2 = save_area[2],			\
+	MR_mr3 = save_area[3],			\
+	(void)0					\
+)
+
+#define MR_save_transient_regs_to_mem(save_area)	((void)0)
+#define MR_restore_transient_regs_from_mem(save_area)	((void)0)
+
+#define	MR_mr4	MR_fake_reg[4]
+#define	MR_mr5	MR_fake_reg[5]
+#define	MR_mr6	MR_fake_reg[6]
+#define	MR_mr7	MR_fake_reg[7]
+#define	MR_mr8	MR_fake_reg[8]
+#define	MR_mr9	MR_fake_reg[9]
+#define	MR_mr10	MR_fake_reg[10]
+#define	MR_mr11	MR_fake_reg[11]
+#define	MR_mr12	MR_fake_reg[12]
+#define	MR_mr13	MR_fake_reg[13]
+#define	MR_mr14	MR_fake_reg[14]
+#define	MR_mr15	MR_fake_reg[15]
+#define	MR_mr16	MR_fake_reg[16]
+#define	MR_mr17	MR_fake_reg[17]
+#define	MR_mr18	MR_fake_reg[18]
+#define	MR_mr19	MR_fake_reg[19]
+#define	MR_mr20	MR_fake_reg[20]
+#define	MR_mr21	MR_fake_reg[21]
+#define	MR_mr22	MR_fake_reg[22]
+#define	MR_mr23	MR_fake_reg[23]
+#define	MR_mr24	MR_fake_reg[24]
+#define	MR_mr25	MR_fake_reg[25]
+#define	MR_mr26	MR_fake_reg[26]
+#define	MR_mr27	MR_fake_reg[27]
+#define	MR_mr28	MR_fake_reg[28]
+#define	MR_mr29	MR_fake_reg[29]
+#define	MR_mr30	MR_fake_reg[30]
+#define	MR_mr31	MR_fake_reg[31]
+#define	MR_mr32	MR_fake_reg[32]
+#define	MR_mr33	MR_fake_reg[33]
+#define	MR_mr34	MR_fake_reg[34]
+#define	MR_mr35	MR_fake_reg[35]
+#define	MR_mr36	MR_fake_reg[36]
+#define	MR_mr37	MR_fake_reg[37]
+
+#endif /* not MR_MACHDEPS_RISCV_REGS_H */
diff --git a/runtime/mercury_regs.h b/runtime/mercury_regs.h
index f7f611a82..67e171018 100644
--- a/runtime/mercury_regs.h
+++ b/runtime/mercury_regs.h
@@ -97,6 +97,8 @@
     #include "machdeps/arm_regs.h"
   #elif defined(__aarch64__)
     #include "machdeps/aarch64_regs.h"
+  #elif defined(__riscv)
+    #include "machdeps/riscv_regs.h"
   #else
     #error "MR_USE_GCC_GLOBAL_REGISTERS not yet supported on this machine."
   #endif
-- 
2.25.1



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